a) Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a method of making a semiconductor device adapted for semiconductor devices with multi-layer wiring.
b) Description of the Related Art
Multi-layer wiring techniques are essential for highly integrated semiconductor devices. It is necessary to electrically insulate wiring layers by an interlayer insulating film. As a lower level wiring pattern is formed, the pattern has inevitably irregular upper surfaces. If the interlayer insulating film is formed conformal to the topology of the underlying layer, similar irregular surfaces are formed on the interlayer insulating film. Some problems of photolithography or patterning a wiring layer occur if an upper level wiring layer is formed on the irregular surfaces of the underlying layer. Therefore, after the lower level wiring pattern is formed, it is desired that recesses between wiring patterns are filled with planarizing material to form an interlayer insulating film having a flat surface.
Various techniques of forming an insulating film having a planarizing function have been developed. However, an insulating film having a planarizing function has generally the tendency that it is inferior to a dense insulating film conformal to the topology of an underlying layer in terms of passivation performance such as water-proof. It is therefore usual that a plurality type of insulating films are stacked to form an interlayer insulating film having a flat surface. One example of such a lamination film will be described.
In patterning a lower level wiring layer, dry etching is generally performed by using a resist pattern as a mask. In dry etching, an unnecessary portion of a wiring layer is fluoridized or chloridized to gasify and remove it, while reaction products are being deposited on the side wall of an etched wiring pattern. These reaction products deposited during etching remain on the side wall of the wiring pattern and on the surface of an insulating film, and become deposition residues. These deposition residues become one of the causes of short circuits between wiring patterns and of defective semiconductor devices. In order to remove such deposition residues, wet etching has been used.
After wet etching, a dense film such as a plasma oxide film which is excellent in passivation performance is formed on the surface of the patterned wiring layer. Such a dense film is deposited conformal to the surface of the underlying layer and has irregular upper surfaces. In order to planarize the irregular surfaces, an insulating film having a planarizing function is formed on the dense film by atmospheric pressure CVD.
If wet etching using organic amine containing liquid is performed so as to remove deposition residues, short circuits and the like to be caused by deposition residues can be prevented. However, the surface topology of the insulating film having the planarizing function and formed through atmospheric pressure CVD is considerably degraded, and even if the insulating film having the planarizing function is formed, a sufficiently planarized surface cannot be formed.